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24AA64/24LC64/24FC64
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Name PDIP SOIC TSSOP
Rotated
TSSOP
DFN (1) TDFN (1) MSOP
SOT-23
CS
Description
A0
A1
A2
V SS
SDA
SCL
WP
V CC
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
3
4
5
6
7
8
1
2
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
—
—
—
2
3
1
5
4
—
—
—
2
5
4
3
1
Chip Address Input
Chip Address Input
Chip Address Input
Ground
Serial Address/Data I/O
Serial Clock
Write-Protect Input
+1.7V to 5.5V Power Supply
Note 1: The exposed pad on the DFN/TDFN packages can be connected to V SS or left floating.
2.1
A0, A1, A2 Chip Address Inputs
2.3
Serial Clock (SCL)
The A0, A1 and A2 inputs are used by the 24XX64 for
multiple device operation. The levels on these inputs
are compared with the corresponding bits in the slave
The SCL input is used to synchronize the data transfer
from and to the device.
address. The chip is selected if the compare is true.
2.4
Write-Protect (WP)
Up to eight devices may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either V CC or V SS .
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘ 0 ’ or logic ‘ 1 ’. For
This pin must be connected to either V SS or V CC . If tied
to V SS , write operations are enabled. If tied to V CC ,
write operations are inhibited but read operations are
not affected.
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
3.0
FUNCTIONAL DESCRIPTION
address pins must be driven to logic ‘ 0 ’ or logic ‘ 1 ’
before normal device operation can proceed. Address
pins are not available in the SOT-23 or Chip Scale
packages.
The 24XX64 supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, while a device
receiving data is defined as a receiver. The bus has to
2.2
Serial Data (SDA)
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an open-
drain terminal, the SDA bus requires a pull-up resistor
to V CC (typical 10 k ? for 100 kHz, 2 k ?? for 400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
? 1997-2012 Microchip Technology Inc.
generates the Start and Stop conditions, while the
24XX64 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
DS21189S-page 5
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